The field of the disclosure relates generally to analog-to-digital converters (ADCs) and, more particularly, to a circuit and method of calibration of radiation-hardened time-interleaved ADCs.
Time-interleaved ADCs are composed of a plurality of ADC units (“slices”) operated in parallel and require calibration to correct for, among other errors, sampling phase mismatch errors between the slices. Least Mean Squares (LMS) methods such as the following are employed for background calibration:
            S      N        ⁡          [              k        +        1            ]        =                    S        N            ⁡              [        k        ]              +          μ      ·                        ⅆ          Y                          ⅆ          k                    ·              Error        ⁡                  [          k          ]                    where SN is a phase adjustment coefficient of calibration stored into an accumulator, μ is the value of the accumulator gain, Y is an ADC slice output value, and k is a sampling time. The SN coefficient is used to numerically tune a DLL (Delay Locked Loop) that precisely controls the time edges of the clock waveforms, and thus the sampling instants, within each ADC slice. Both ADC implementations with a single, common multi-tap DLL driving all slices, and implementations where each slice contains instead its own local DLL are equally operational, making this aspect not functional to the invention. Calibration thus requires two registers: to retain memory of the previous ADC slice output value, and of the current ADC slice output value (under calibration). The time derivative approximation dY/dk is imprecise in many known calibration methods, and under certain conditions it potentially leads to incorrect evolution direction and significant error propagation, leading to divergence of the calibration process to the point of system failure. Such negative effects are worsened in closed-loop LMS-based calibration methods under, e.g., radiation conditions that cause single-event upsets (SEUs) in digital cells, due to heavy ion single-event effects (SEEs). Also, circuit implementations of ever increasing cost and complexity are required in modern applications demanding sampling frequencies into gigahertz (GHz) ranges, 10 bits or greater resolution, and phase calibration step sizes of the DLL down to 50 femtoseconds (fs) and below. As such, merely lowering the ADC input frequencies is no longer enough to resolve the aforementioned problems when calibrating time-interleaved ADCs, and designers face continued challenges meeting demands of modern applications exacerbated by SEU and SEE conditions.